Apparatus and method for reducing power consumption within an oscillator
US7280000B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0231
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oscillator according to the present invention reduces power consumption by enlarging the pulsewidth of an oscillator output pulse. Since this pulse disables an oscillator current source, the enlarged pulsewidth reduces the time the current source is enabled. When a first capacitor charges to at least a reference voltage, a differential amplifier produces a low level signal that is provided to a latch generating the output pulse. The low level signal controls the latch to produce and maintain a high level signal until the latch is triggered. The latch signal disables the current source, while enabling a transistor to transfer charge from the first capacitor to a second capacitor. When the second capacitor attains a sufficient voltage, the latch is triggered to produce a low level signal, thereby enlarging the pulsewidth of the output pulse. The low level signal enables the current source and facilitates discharge of the second capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.