Reducing sneak currents in virtual ground memory arrays
US7280400B2 · kind B2 · utility
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24Claims
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Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Oct 9, 2007 |
| Priority date | — |
| Expiry date | Oct 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0491
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The sneak currents may arise when cells in each of two adjacent I/O groups are sensed (or programmed) at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.