Semiconductor memory devices having offset transistors and methods of fabricating the same
US7282761B2 · kind B2 · utility
9Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2003 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Oct 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include word lines. One of these word lines may form the gate of the second planar transistor a unit memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.