Image sensing chip package structure
US7282788B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In an image sensing chip package structure, plated through vias penetrate a substrate to electrically connect metallization traces disposed on the upper and lower surfaces of the substrate. The plated through vias can be opened from the center of the substrate instead of being located at the periphery of the substrate. Contamination can thus be avoided during the glue dispensing process, and protection layers can also be used to seal gaps generated by the plated through vias, hence enhancing the producing yield. Moreover, protection layers having stickiness can further be used to secure components so as to reduce the production cost and enhance the product quality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.