Processor that predicts floating point instruction latency based on predicted precision
US7284117B1 · kind B1 · utility
34Cited by
5References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 4, 2003 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Jan 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4876
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is configured to detect a misprediction of the execution latency. In some embodiments, an exception may be taken in response to the misprediction. In other embodiments, the floating point operation may be rescheduled with the corrected execution latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.