Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device
US7284144B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2002 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.