Inventor · Milano, IT

Stefano Surico

22Patents
5h-index
22Co-inventors
65Inventor score

Filing activity: Dec 4, 2002 → Mar 27, 2014

Most-cited inventions

PatentTitleAreaCited byStatus
US7417904B2 Adaptive gate voltage regulation Physics 31 Active
US7249215B2 System for configuring parameters for a flash memory Physics 21 Active
US7181565B2 Method and system for configuring parameters for flash memory Physics 15 Expired
US7158415B2 System for performing fast testing during flash reference cell setting Physics 11 Expired
US7284144B2 Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device Physics 5 Expired
US8705283B2 Erase techniques and circuits therefor for non-volatile memory devices Physics 2 Active
US7302518B2 Method and system for managing a suspend request in a flash memory Physics 2 Expired
US8884666B2 Clock generator Physics 2 Active
US7570519B2 Method and system for program pulse generation during programming of nonvolatile electronic devices Physics 2 Expired
US7525856B2 Apparatus and method to manage external voltage for semiconductor memory testing with serial interface Physics 2 Active
US8120963B2 Method and system for program pulse generation during programming of nonvolatile electronic devices Physics 1 Active
US7864583B2 Erase verify for memory devices Physics 1 Active
US7589572B2 Method and device for managing a power supply power-on sequence Physics 1 Active
US7769943B2 Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory Physics 1 Active
US9349480B2 Erase techniques and circuits therefor for non-volatile memory devices Physics 1 Active
US8553460B2 Method and system for program pulse generation during programming of nonvolatile electronic devices Physics 0 Active
US8779811B2 Clock generator General 0 Revoked
US7551498B2 Implementation of column redundancy for a flash memory with a high write parallelism Physics 0 Active
US8456917B1 Logic circuit for a semiconductor memory device, and method of managing an operation in the semiconductor memory device Electricity 0 Active
US7404049B2 Method and system for managing address bits during buffered program operations in a memory device Physics 0 Expired
US7447071B2 Low voltage column decoder sharing a memory array p-well Physics 0 Active
US7345921B2 Method and system for a programming approach for a nonvolatile electronic device Physics 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.