Method and system for testing RAM redundant integrated circuits
US7284168B2 · kind B2 · utility
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11References
18Claims
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Key dates
| Filing date | Jan 26, 2005 |
| Grant date | Oct 16, 2007 |
| Priority date | — |
| Expiry date | Nov 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.