Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film
US7285862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2004 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1189
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.