Pad structures including insulating layers having a tapered surface
US7285863B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2004 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Nov 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.