Bit line sharing and word line load reduction for low AC power SRAM architecture
US7286383B1 · kind B1 · utility
5Cited by
17References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 10, 2002 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Aug 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduced by sharing bit lines of adjacent bit cells. Furthermore, in order to achieve power saving, the load on the row select lines is reduced by sharing the pass gates between adjacent bit cells that are used to control precharging, reading from and writing to the bit cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.