Three dimensional twisted bitline architecture for multi-port memory
US7286437B2 · kind B2 · utility
9Cited by
10References
15Claims
0Family size
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Key dates
| Filing date | Jun 17, 2005 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Sep 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.