SRAM based cache for DRAM routing table lookups
US7286534B2 · kind B2 · utility
50Cited by
9References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | May 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/54
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A router (101) includes one or more input ports (104) and one or more output ports (112). The router (101) includes a lookup table (105) to determine routing of the incoming packets or cells. The lookup table is implemented in dynamic random access memory (DRAM) with a portion implemented as static random access memory (SRAM) (202, 204). The SRAM (204) is used to store a first search level of destination addresses. Once the first search level in SRAM (204) has been exhausted, the search moves to the DRAM portion (202).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.