Aligned logic cell grid and interconnect routing architecture
US7287237B2 · kind B2 · utility
5Cited by
6References
10Claims
0Family size
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Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Oct 23, 2007 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for defining an aligned logic cell grid and interconnect layout of a semiconductor integrated circuit having a logic cell is disclosed. The interconnect layout is resized in accordance with a highest common denominator of an initial routing pitch of the interconnect layout and a transistor pitch of the logic cell. The cell grid is aligned with the resized routing pitch which provides efficient routing density and transistor performance, minimizes excess transistor area and wire routing waste while maximizing cell packing density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.