Method for reducing defects after a metal etching in semiconductor devices
US7288427B2 · kind B2 · utility
0Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Sep 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method prevents oxidation or contamination phenomena of conductive interconnection structures in semiconductor devices and includes providing a layer of semiconductor or oxide base, a conductive layer or stack on the base layer, and an antireflection coating (ARC) layer on the conductive layer or stack. The method provides a thin dielectric covering layer on the antireflection coating layer to fill or cover the microfissures existing in the antireflection coating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.