Semiconductor memory with virtual ground architecture
US7288812B2 · kind B2 · utility
4Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 2004 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Jul 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Insulation regions in the manner of STI isolations, which run transversely with respect to the word lines, isolate the source/drain regions of adjacent memory cells. Metallic bit lines are applied on the top side and patterned for example along zigzag lines such that the source/drain regions of a memory transistor which are contact-connected by the bit lines are in each case electrically connected by two mutually adjacent bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.