DRAM hierarchical data path
US7289369B2 · kind B2 · utility
8Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Apr 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.