High performance implementation of exponent adjustment in a floating point design
US7290023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Dec 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.