Cache memory to support a processor's power mode of operation
US7290093B2 · kind B2 · utility
3Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2003 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and apparatus for a cache memory to support a low power mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.