Methods and apparatus for reducing memory errors
US7290185B2 · kind B2 · utility
6Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a first aspect, a first method is provided for reducing memory errors. The first method includes the steps of (1) detecting at least one error in data output from a first physical memory unit (PMU) of a memory; (2) detecting at least one error in data output from a second PMU of the memory; and (3) setting a bit indicating respective data output from a plurality of PMUs includes errors. Numerous other aspects are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.