Hardware accelerator with a single partition for latches and combinational logic
US7290228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Oct 30, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator includes hardware support for a combinational only cycle and a latch only cycle in a simulation model with a single partition of latches and combinational logic. Preferred embodiments use a special 4-input 1-output function unit in the hardware accelerator in place of the normal latch function that write back the old latch value for combinational only cycles. Other embodiments include hardware support for separate array write disables for arrays and transparent latches depending on whether the cycle is a combinational only cycle and a latch only cycle. A conditional array write disable dependent on the occurrence of a hardware breakpoint is also included that supports switching from a latch plus combinational cycle to a latch only cycle, to give control to the user before evaluating the combinational logic if a breakpoint occurs on a latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.