Semiconductor device and method of manufacture thereof
US7291526B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dielectric material layer is formed over a workpiece, a metal layer is formed over the dielectric material layer, and a semiconductive material layer is formed over the metal layer. The workpiece is heated, causing a top portion of the metal layer to interact with the semiconductive material layer and causing a bottom portion of the metal layer to diffuse into the dielectric material layer. The metal layer portion that interacts with the semiconductive material layer forms a silicide, and the diffused metal layer portion forms a high dielectric constant gate material having a graded concentration of the metal from the metal layer. At least the semiconductive material layer and the dielectric material layer are patterned to form a gate and a gate dielectric of a transistor device. A source region and a drain region are formed in the workpiece proximate the gate and gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.