Semiconductor device and method of manufacturing thereof
US7291929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A connection method is disclosed for a high-performance semiconductor system. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. Semiconductor chips and the interposer chips are polished by grinding at their rear surfaces, holes are formed at rear surface positions corresponding to external electrode parts on the device side (front surface side) so that the holes extend to front surface electrodes, and metal plating films are applied to the side walls of the holes and rear surface side. Metal bumps of another semiconductor chip laminated at an upper stage being press-fitted into the holes applied with the metal plating films through deformation and being geometrically calked in the through holes formed in the semiconductor chip so as to electrically connected thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.