Data communication system with hardware protocol parser and method therefor
US7293113B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Nov 6, 2007 |
| Priority date | — |
| Expiry date | Sep 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communication processor comprises a data link layer parser circuit (310) and a plurality of network layer parser circuits (322, 326). The data link layer parser circuit (310) receives a data link layer frame, and removes a data link layer header therefrom to provide a network layer frame as an output. Each network layer parser circuit corresponds to a different network layer protocol, and is selectively activated to receive the network layer frame and to process a network layer header therefrom to provide a transport layer frame as an output. The data link layer parser circuit (310) further examines a portion of the network layer frame to determine which of the plurality of network protocols is used. The data link layer parser circuit (310) activates a corresponding one of the plurality of network layer parser circuits (322, 326) in response, while keeping another one of the plurality of network layer parser circuits (322, 326) inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.