Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure

US7294564B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Wilfried Attenberger · Landshut, DE
• Jörg Lindner · Bobingen, DE
• Bernd Stritzker · Kissing, DE

Key dates

• Filing date: Oct 11, 2002
• Grant date: Nov 13, 2007
• Expiry date: Sep 10, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10H20/018
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said layer of said first semiconductor material in said substrate, said buried layer having an upper surface and a lower surface and dividing said substrate into an upper part and a lower part; creating a buried damage layer; which at least partly adjoins and/or partly includes said upper surface of said buried layer; and removing said upper part of said substrate and said buried damage layer for exposing said buried layer. The invention also provides a corresponding layered semiconductor structure.