Method and circuit for writing double data rate (DDR) sampled data in a memory device
US7295489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2005 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.