Method to locate logic errors and defects in digital circuits
US7296201B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2005 |
| Grant date | Nov 13, 2007 |
| Priority date | — |
| Expiry date | May 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more inputs of the assertion circuit are identified as potentially the source of the error, the process of backtracing is performed for each such input. When the input that is potentially the source of the error emanates from a memory circuit, the fanin cone of the memory circuit is identified and the process of backtracing through the last-identified fanin cone is undertaken for clock k−1. This is repeated iteratively until either a module of the integrated circuit is found to be the source of the error, or the error is extended to inputs of the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.