Structure and method of making sealed capped chips
US7298030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Apr 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/857
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.