Stacked semiconductor device
US7298045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Apr 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.