System and method for power on reset and under voltage lockout schemes
US7298187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2006 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jun 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.