1T1R resistive memory array with chained structure
US7298640B2 · kind B2 · utility
123Cited by
5References
5Claims
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Key dates
| Filing date | May 3, 2005 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.