Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states
US7299370B2 · kind B2 · utility
12Cited by
16References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Nov 20, 2007 |
| Priority date | — |
| Expiry date | Jan 18, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.