Semiconductor memory device comprising controllable threshould voltage dummy memory cells
US7301815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Jul 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.