Algorithm pattern generator for testing a memory device and memory tester using the same
US7302623B2 · kind B2 · utility
8Cited by
7References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.