System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
US7302659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2005 |
| Grant date | Nov 27, 2007 |
| Priority date | — |
| Expiry date | Feb 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.