Bradley Nelson
22Patents
7h-index
18Co-inventors
62Inventor score
Filing activity: Apr 28, 2003 → Nov 27, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7089518B2 | Method and program product for modelling behavior of asynchronous clocks in a system having multiple clocks | Physics | 32 | Expired |
| US7484192B2 | Method for modeling metastability decay through latches in an integrated circuit model | Physics | 23 | Active |
| US7299436B2 | System and method for accurately modeling an asynchronous interface using expanded logic elements | Physics | 23 | Expired |
| US7484196B2 | Method for asynchronous clock modeling in an integrated circuit simulation | Physics | 22 | Active |
| US7877717B2 | Accurately modeling an asynchronous interface using expanded logic elements | Physics | 20 | Active |
| US6993729B2 | Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model | Physics | 11 | Expired |
| US7995619B2 | Methods and arrangements to model an asynchronous interface | Physics | 10 | Active |
| US8627047B2 | Store data forwarding with no memory model restrictions | Physics | 7 | Active |
| US7302659B2 | System and method for unfolding/replicating logic paths to facilitate propagation delay modeling | Physics | 7 | Expired |
| US7536288B2 | Method, system and program product supporting user tracing in a simulator | Physics | 6 | Expired |
| US10318435B2 | Ensuring forward progress for nested translations in a memory management unit | Physics | 5 | Active |
| US8238190B2 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Physics | 5 | Active |
| US7447620B2 | Modeling asynchronous behavior from primary inputs and latches | Physics | 5 | Active |
| US7870528B2 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Physics | 4 | Active |
| US7448015B2 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation | Physics | 3 | Active |
| US7453759B2 | Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic | Physics | 2 | Active |
| US7426461B2 | Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities | Emerging Cross-Sectional Technologies | 1 | Expired |
| US7885801B2 | Modeling asynchronous behavior from primary inputs and latches | Physics | 1 | Active |
| US7519524B2 | Program product for providing a configuration specification language supporting incompletely specified configuration entities | Emerging Cross-Sectional Technologies | 1 | Active |
| US8468306B2 | Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions | Physics | 0 | Active |
| US10380031B2 | Ensuring forward progress for nested translations in a memory management unit | Physics | 0 | Active |
| US8984261B2 | Store data forwarding with no memory model restrictions | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.