Patent · US Expired

System and method for automatic insertion of on-chip decoupling capacitors

US7302664B2 · kind B2 · utility

8Cited by

3References

17Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Anand Haridass · Bengaluru, IN
Andreas Huber · Holzgerlingen, DE
Erich Klink · Schenefeld, DE
Jochen Supper · Herrenberg, DE

Key dates

Filing date	Feb 10, 2005
Grant date	Nov 27, 2007
Priority date	—
Expiry date	Jan 16, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.