Copper electrodeposition in microelectronics
US7303992B2 · kind B2 · utility
17Cited by
29References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Nov 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.