High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics
US7303996B2 · kind B2 · utility
8Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Nov 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.