Structure of sequencers that perform initial and periodic calibrations in a memory system
US7305517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Nov 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.