Nonvolatile memory and nonvolatile memory apparatus
US7305596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.