Serial implementation of assertion checking logic circuit
US7305635B1 · kind B1 · utility
18Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Feb 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Serial assertion checking is realized in a System On a Chip (SoC) device by connecting scan chain output to a bit extractor configured within a functionally reconfigurable module that is part of the SoC, which extracts the bits necessary for the assertion checking. The extracted bits are applied to a finite state machine that implements the assertion checking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.