Method of tiling analog circuits
US7305642B2 · kind B2 · utility
0Cited by
10References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2005 |
| Grant date | Dec 4, 2007 |
| Priority date | — |
| Expiry date | Sep 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.