Method of forming a multi-layer semiconductor structure incorporating a processing handle member
US7307003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jan 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.