Methods of forming integrated circuit devices including a multi-layer poly film cell pad contact hole
US7307008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.