Control of strain in device layers by selective relaxation
US7307273B2 · kind B2 · utility
55Cited by
212References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Dec 2, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.