EEPROM with etched tunneling window
US7307309B2 · kind B2 · utility
2Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Apr 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.