Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device
US7307333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2002 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Nov 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.