Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
US7307885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Feb 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.