Reducing power consumption in integrated circuits
US7307899B2 · kind B2 · utility
18Cited by
1References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2005 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Jul 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.